We have previously disclosed a method of fabricating a metal/ferroelectric/metal (MFM) gate stack on a semiconductive metal oxide on a silicon structure, In2O3 thin films resistivity control by doping metal oxide insulator for MFMox device applications, U.S. patent application Ser. No. 10/755,419, filed Jan. 12, 2004, and of fabricating a MFM gate stack on semiconductive metal oxide on silicon substrate structure, Conductive metal oxide gate ferroelectric memory transistor, U.S. Patent Publication No. 2005/0054166 A1 of Hsu et al., published Mar. 10, 2005. These two device structures, however, do not have floating gate structures, which structures result in a potentially long memory retention time. The integration processes for fabricating metal oxide ferroelectric memory transistors require precise fabrication procedures, particularly in the deposition and annealing steps during fabrication of a semiconductive metal oxide on a silicon substrate, and in ferroelectric thin film deposition and annealing processes. By optimizing the integration processes, a working 1T MFMox memory device is efficiently fabricated.